1. Field of the Invention
The present invention relates to a semiconductor package. More particularly, the present invention relates to a dual leadframe package.
2. Description of the Related Art
As chip integration increases, various semiconductor packages are used, such as a chip scale package or a multi-chip module, for example. However, a leadframe is usually used for packaging a low pin count chip such as a high-voltage device.
FIG. 1 is a schematic, cross-sectional view of a conventional low pin count semiconductor package.
Referring to FIG. 1, a chip 12 is attached to a bonding pad 10 and coupled to a lead 18 through a wire 14 formed by wire bonding. The chip 12, the wire 14, the bonding pad 10 and a portion of the lead 18 are sealed by a packaging material 16. The packaging material 16 fixes the relative position of the chip 12, the bonding pad 10, the wire 14 and the lead 18 and protects the chip 12. A portion of the lead 18 exposed is bent downward for coupling to a printed circuit board. Additionally, the lead 18 can be formed in a gull wing shape to couple to the printed circuit board through a surface mount technique.
In the conventional packaging process, many steps are needed and many kinds of machines are needed to perform the steps. Furthermore, it is time-consuming to perform the wire bonding process. The manufacturing time and the manufacturing cost are high. It is difficult to increase throughput.
The signal transmitting path including the lead and the wire is long, so that impedance may increase, and signal decay and signal delay may occur. The package structure properties do not satisfy the requirement of the chip. For example, in 0.4 .mu.m MOS, the resistance of the chip is 0.2 m.OMEGA.-cm. However, the resistance of the chip scale package is 20 m.OMEGA.-cm, so that the performance of the chip is seriously affected. Moreover, the volume of the package is large. The large volume restricts the application of the chip.